1. Field of the Invention
The present invention relates to a method for plating an integrated circuit package.
2. Description of Related Art
Integrated circuits are typically protected by a package that is soldered to a printed circuit board. There have been developed various types of packages including gull-wing, pin grid array and a package commonly referred to as "C4" or "flip chip". Flip chip packages include an integrated circuit die that is surface mounted to a substrate of the package. The integrated circuit is provided with a plurality of solder bumps that extend from the die pads of the die. The die and solder bumps are placed onto corresponding contact pads of the substrate. The solder bumps are then reflowed to connect the die pads to the contact pads. Extending from a bottom surface of the substrate are a plurality of pins that can be soldered to the printed circuit board.
The contact pads and pins of the substrate are typically constructed from tungsten and copper material, respectively. A layer of gold is plated onto the pins and pads to inhibit corrosion of the tungsten and copper material. An intermediate layer of nickel-phosphorus (Ni--P) is initially plated onto the copper and tungsten to increase the adhesion of the gold. It has been found that the nickel-phosphorus will create a relatively brittle solder joint at the bump sites of a flip chip package. Brittle solder joints tend to crack and reduce the integrity of the package assembly. It would be desirable to provide a flip chip package which has a more ductile bump solder joint than packages of the prior art.